1. Field of the Invention
The present invention relates to power supply voltage step-down circuitry for decreasing the voltage of a power supply and for supplying the decreased voltage to a receiver.
2. Description of the Prior Art
Referring now to FIG. 9, there is illustrated a schematic circuit diagram showing the structure of prior art power supply voltage step-down circuitry. In the figure, reference numeral 1 denotes a current supply circuit, numeral 2 denotes a pull-up circuit, numeral 3 denotes a circuit, such as a ROM, which is the receiver of power supply voltage generated by the prior art power supply voltage step-down circuitry, and numeral 4 denotes a control circuit. The circuit 3 will be referred to as a target circuit in this specification. Further, reference numeral 10 denotes a power supply, numeral 11 denotes a comparator, numeral 12 denotes a P-channel transistor having a source connected to the power supply 10, a drain connected to an output 13 of the current supply circuit 1, and a gate connected to an output of the comparator 11, numeral 21 denotes a resistor having an end connected to the power supply 10, and numeral 22 denotes a switch having an end connected to the other end of the resistor 21 and another end connected to a power supply 31 of the target circuit 3. The comparator 11 has an input to which a reference voltage is applied and another input connected to both the drain of the P-channel transistor 12 and the output 13 of the current supply circuit 1. The comparator 11 of the current supply circuit 1 has a control terminal 111 to receive a comparator enable signal from the control circuit 4. The power supply 10 is connected to the comparator 11 (the connection is not shown in FIG. 9). The switch 22 of the pull-up circuit 2 has a control terminal 221 to receive a pull-up circuit enable signal from the control circuit 4.
The power supply voltage step-down circuit, as shown in FIG. 9, can be incorporated into a microcomputer, for example, and serve to supply a 3-V power supply voltage to a ROM in order to activate the ROM together with a ROM peripheral circuit that can run from 5-V supply. In this case, the power supply voltage step-down circuit generates a 3-V power supply voltage by decreasing the output voltage of the power supply 10 and then supplies the 3-V power supply voltage to the ROM that can run from 3-V supply while the 5-V power supply 10 directly applies its output voltage to the ROM peripheral circuit that can run from 5-V supply.
In general, although prior art power supply voltage step-down circuitry can supply a decreased voltage having a certain value, which has been generated from the output of the power supply 10, to the target circuit 3 such as a ROM, the decreased voltage tends to decrease with an increase in the output current and to increase with a decrease in the output current. To eliminate the drawback, the prior art power supply voltage step-down circuitry can use a method of detecting changes in the decreased voltage, and increasing the decreased voltage with a decrease in the decreased voltage or further decreasing the decreased voltage with an increase in the decreased voltage. Using the method, the prior art power supply voltage step-down circuitry can supply a decreased voltage having a constant value.
Dividing the prior art power supply voltage step-down circuitry broadly into parts, the prior art power supply voltage step-down circuitry is comprised of the current supply circuit 1 and the pull-up circuit 2, as shown in FIG. 9. Either the output 13 of the current supply circuit 1 or the output 23 of the pull-up circuit 2 can be connected to the power supply 31 of the target circuit 3, such as a ROM, which runs from the decreased voltage from the prior art power supply voltage step-down circuitry. The current supply circuit 1 generates and furnishes the decreased voltage to the target circuit 3 when the target circuit 3 is held in a normal state. When the target circuit 3 is held in a normal state and the comparator 11 is enabled after the control circuit 4 has asserted and furnished the comparator enable signal to the control terminal 111 of the comparator 11, the current supply circuit 1 can keep its output 13 at a certain voltage. To be more specific, when the voltage of the output 13 of the current supply circuit 1 exceeds the reference voltage, the output of the comparator 11 increases in voltage. As a result, the P-channel transistor 12 switches to the off state and the voltage that appears at the drain of the P-channel transistor 12 drops, and therefore the voltage of the output 13 of the current supply circuit 1 drops. In contrast, when the voltage of the output 13 of the current supply circuit 1 becomes lower than the reference voltage, the output voltage of the comparator 11 drops. As a result, the P-channel transistor 12 switches to the on state and the voltage that appears at the drain of the P-channel transistor 12 increases, and therefore the output 13 of the current supply circuit 1 increases in voltage. This feedback control makes it possible for the current supply circuit 1 to keep its output 13 at a certain voltage by sensing any variation in the voltage of the output 13 and changing the output voltage back to its original value. Since the comparator 11 can give a quick response to changes in the input connected to the output 13, and therefore any variation in the input can quickly cause a change in the output of the comparator, the current supply circuit 1 can quickly correct the decreased voltage.
In this way, the current supply circuit 1 can supply a large amount of current to the target circuit 3 while, even if the decreased voltage applied to the target circuit 3 that consumes the current fed thereto from the current supply circuit 1 varies, the current supply circuit 1 can quickly correct the decreased voltage to prevent any variation in the decreased voltage. In contrast, the current supply circuit 1 has the disadvantage of high current consumption.
On the other hand, when the target circuit 3 is held in a standby state, the control circuit 4 negates the comparator enable signal, and therefore the comparator 11 furnishes an output having a voltage at a power supply voltage level. As a result, the P-channel transistor 12 is brought into a floating state and hence the output 13 of the current supply circuit 1 is also brought into a floating state.
The pull-up circuit 2 generates a decreased voltage when the current consumption in the target circuit 3 is very small, such as when the target circuit 3 is held in a standby state. When the target circuit 3 is held in a standby state, dissipation current flowing through the target circuit 3 is very small and few variations occur in the dissipation current. There can be a constant voltage drop due to the dissipation current flowing through the target circuit 3 in the resistor 21 of the pull-up circuit 2. As a result, the decreased voltage, which is obtained by subtracting the voltage drop from the voltage of the power supply 10, is supplied to the power supply 31 of the target circuit 3.
To be more specific, when the target circuit 3 is held in a standby state, the control circuit 4 asserts the pull-up circuit enable signal (at the same time, the comparator enable signal is negated). As a result, the power supply 10, the resistor 21, the switch 22, and the output 23 of the pull-up circuit are electrically connected to each other. Since the dissipation current flowing through the target circuit 3 is very small and is almost constant when the target circuit 3 is held in a standby state, a constant voltage drop occurs in the resistor 21 of the pull-up circuit 2 due to the dissipation current. As a result, a voltage that is equal to (the voltage of the power supply 10--the voltage drop) appears at the output 23 of the pull-up circuit and is then applied to the power supply 31 of the target circuit 3. Accordingly, by setting the resistance value of the resistor 21 so that the decreased voltage that appears at the output 23 of the pull-up circuit has a desired value, the prior art power supply voltage step-down circuitry can supply the decreased voltage having the desired value to the target circuit 3 even when the target circuit 3 is held in a standby state.
As shown in FIG. 9, the control circuit 4 has an output connected to both the control terminal 111 of the comparator 11 of the current supply circuit 1 and the control terminal 221 of the switch 22 of the pull-up circuit 2. When the target circuit 3 is held in a normal state, the control circuit 4 furnishes a signal at a power supply voltage level. In contrast, when the target circuit 3 is held in a standby state, the control circuit 4 furnishes a signal at a ground level. When the comparator enable signal is at a power supply voltage level, the comparator 11 of the current supply circuit 1 is enabled. When the pull-up circuit enable signal is at a ground level, the switch 22 of the pull-up circuit 2 is enabled. As previously mentioned, when the target circuit 3 is held in a normal state, the comparator 11 of the current supply circuit 1 is enabled. In contrast, when the target circuit 3 is held in a standby state, the switch 22 of the pull-up circuit 2 is closed. Referring next to FIG. 10, there is illustrated a schematic circuit diagram showing the structure of an example of the control circuit 4 of the prior art power supply voltage step-down circuitry. In the figure, reference numeral 41 denotes an inverter. As shown in FIG. 10, the control circuit 4 is constructed of the inverter 41 to receive a stop signal, and the output of the inverter 41 serves as the output of the control circuit 4. For example, when a microcomputer executes a stop instruction, the target circuit 3 is brought into a standby state. In this case, since the stop signal has a power supply voltage level and hence the output of the control circuit 4 has a ground level, the current supply circuit 1 is disabled and the pull-up circuit 2 is enabled.
A microcomputer into which the prior art power supply voltage step-down circuitry as mentioned above is incorporated uses the output 13 or 23 which has been obtained by decreasing the voltage of the power supply 10. Accordingly, a problem with the prior art power supply voltage step-down circuitry is that since, when the voltage of the power supply 10 is low, the power supply 31 of the target circuit 3 has a lower voltage, a margin of low-voltage operating conditions becomes small. To solve the problem, Japanese Patent Application Publication (KOKAI) No.8-211954 discloses power supply voltage step-down circuitry for directly using an external voltage as an internal voltage to be applied to a target circuit, such as a ROM, without having to use a voltage step-down circuit, when the external voltage is equal to or less than a reference voltage.
Referring next to FIG. 11, there is illustrated a schematic circuit diagram showing the prior art power supply voltage step-down circuitry as disclosed in Japanese Patent Application Publication (KOKAI) No. 8-211954. In the figure, reference numeral 10 denotes a power supply, numeral 31 denotes a P-channel transistor, numeral 32 denotes a voltage checking circuit for sensing the voltage of the power supply 10 and for comparing the sensed voltage with a reference voltage, numerals 33 and 34 denote transmission gates, numeral 35 denotes a voltage step-down circuit for decreasing the voltage of the power supply 10 and for furnishing the decreased voltage, and 36 denotes a control circuit for disabling the voltage step-down circuit 35 when the voltage of the power supply 10 is lower than the reference voltage.
In operation, the voltage checking circuit 32 having a 4-V threshold voltage (or reference voltage) senses the voltage of the power supply 10 when the voltage step-down circuit 35 and the P-channel transistor 31 decrease the voltage of the power supply 10 which can vary in the range of 0 to 5 volts to generate a 3-V internal voltage Vint. When the voltage of the power supply 10 is equal to or less than 4 volts, the voltage checking circuit 32 applies its output to the P-channel transistor 31 by way of the transmission gate 33 to control the P-channel transistor 31. In this case, the P-channel transistor 31 is brought into the on state, and therefore the voltage of the power supply 10, which is the source voltage, becomes Vint. In contrast, when the voltage of the power supply 10 exceeds 4 volts, the voltage step-down circuit 35 applies its output to the P-channel transistor 31 by way of the transmission gate 34. In this case, a decreased voltage from the voltage step-down circuit 35 becomes Vint. Therefore, the prior art power supply voltage step-down circuitry, as shown in FIG. 11, has a disadvantage in that when the voltage of the power supply 10 has a value which is close to the 4-V threshold voltage, the internal voltage Vint becomes unstable. In addition, since the voltage checking circuit disposed within the prior art power supply voltage step-down circuitry checks whether the voltage of the power supply exceeds the threshold voltage at all times, the current consumption in the prior art power supply voltage step-down circuitry is large.